#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar_trm.inc

/* UART_rx */
UART_rx__0__DM__MASK EQU 0x7000
UART_rx__0__DM__SHIFT EQU 12
UART_rx__0__DR EQU CYREG_PRT0_DR
UART_rx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
UART_rx__0__HSIOM_MASK EQU 0x000F0000
UART_rx__0__HSIOM_SHIFT EQU 16
UART_rx__0__INTCFG EQU CYREG_PRT0_INTCFG
UART_rx__0__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_rx__0__MASK EQU 0x10
UART_rx__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_rx__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_rx__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_rx__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_rx__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_rx__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_rx__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_rx__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_rx__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_rx__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_rx__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_rx__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_rx__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_rx__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_rx__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_rx__0__PC EQU CYREG_PRT0_PC
UART_rx__0__PC2 EQU CYREG_PRT0_PC2
UART_rx__0__PORT EQU 0
UART_rx__0__PS EQU CYREG_PRT0_PS
UART_rx__0__SHIFT EQU 4
UART_rx__DR EQU CYREG_PRT0_DR
UART_rx__INTCFG EQU CYREG_PRT0_INTCFG
UART_rx__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_rx__MASK EQU 0x10
UART_rx__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_rx__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_rx__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_rx__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_rx__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_rx__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_rx__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_rx__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_rx__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_rx__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_rx__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_rx__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_rx__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_rx__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_rx__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_rx__PC EQU CYREG_PRT0_PC
UART_rx__PC2 EQU CYREG_PRT0_PC2
UART_rx__PORT EQU 0
UART_rx__PS EQU CYREG_PRT0_PS
UART_rx__SHIFT EQU 4

/* UART_SCB */
UART_SCB__BIST_CONTROL EQU CYREG_SCB1_BIST_CONTROL
UART_SCB__BIST_DATA EQU CYREG_SCB1_BIST_DATA
UART_SCB__CTRL EQU CYREG_SCB1_CTRL
UART_SCB__EZ_DATA00 EQU CYREG_SCB1_EZ_DATA00
UART_SCB__EZ_DATA01 EQU CYREG_SCB1_EZ_DATA01
UART_SCB__EZ_DATA02 EQU CYREG_SCB1_EZ_DATA02
UART_SCB__EZ_DATA03 EQU CYREG_SCB1_EZ_DATA03
UART_SCB__EZ_DATA04 EQU CYREG_SCB1_EZ_DATA04
UART_SCB__EZ_DATA05 EQU CYREG_SCB1_EZ_DATA05
UART_SCB__EZ_DATA06 EQU CYREG_SCB1_EZ_DATA06
UART_SCB__EZ_DATA07 EQU CYREG_SCB1_EZ_DATA07
UART_SCB__EZ_DATA08 EQU CYREG_SCB1_EZ_DATA08
UART_SCB__EZ_DATA09 EQU CYREG_SCB1_EZ_DATA09
UART_SCB__EZ_DATA10 EQU CYREG_SCB1_EZ_DATA10
UART_SCB__EZ_DATA11 EQU CYREG_SCB1_EZ_DATA11
UART_SCB__EZ_DATA12 EQU CYREG_SCB1_EZ_DATA12
UART_SCB__EZ_DATA13 EQU CYREG_SCB1_EZ_DATA13
UART_SCB__EZ_DATA14 EQU CYREG_SCB1_EZ_DATA14
UART_SCB__EZ_DATA15 EQU CYREG_SCB1_EZ_DATA15
UART_SCB__EZ_DATA16 EQU CYREG_SCB1_EZ_DATA16
UART_SCB__EZ_DATA17 EQU CYREG_SCB1_EZ_DATA17
UART_SCB__EZ_DATA18 EQU CYREG_SCB1_EZ_DATA18
UART_SCB__EZ_DATA19 EQU CYREG_SCB1_EZ_DATA19
UART_SCB__EZ_DATA20 EQU CYREG_SCB1_EZ_DATA20
UART_SCB__EZ_DATA21 EQU CYREG_SCB1_EZ_DATA21
UART_SCB__EZ_DATA22 EQU CYREG_SCB1_EZ_DATA22
UART_SCB__EZ_DATA23 EQU CYREG_SCB1_EZ_DATA23
UART_SCB__EZ_DATA24 EQU CYREG_SCB1_EZ_DATA24
UART_SCB__EZ_DATA25 EQU CYREG_SCB1_EZ_DATA25
UART_SCB__EZ_DATA26 EQU CYREG_SCB1_EZ_DATA26
UART_SCB__EZ_DATA27 EQU CYREG_SCB1_EZ_DATA27
UART_SCB__EZ_DATA28 EQU CYREG_SCB1_EZ_DATA28
UART_SCB__EZ_DATA29 EQU CYREG_SCB1_EZ_DATA29
UART_SCB__EZ_DATA30 EQU CYREG_SCB1_EZ_DATA30
UART_SCB__EZ_DATA31 EQU CYREG_SCB1_EZ_DATA31
UART_SCB__I2C_CFG EQU CYREG_SCB1_I2C_CFG
UART_SCB__I2C_CTRL EQU CYREG_SCB1_I2C_CTRL
UART_SCB__I2C_M_CMD EQU CYREG_SCB1_I2C_M_CMD
UART_SCB__I2C_S_CMD EQU CYREG_SCB1_I2C_S_CMD
UART_SCB__I2C_STATUS EQU CYREG_SCB1_I2C_STATUS
UART_SCB__INTR_CAUSE EQU CYREG_SCB1_INTR_CAUSE
UART_SCB__INTR_I2C_EC EQU CYREG_SCB1_INTR_I2C_EC
UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB1_INTR_I2C_EC_MASK
UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB1_INTR_I2C_EC_MASKED
UART_SCB__INTR_M EQU CYREG_SCB1_INTR_M
UART_SCB__INTR_M_MASK EQU CYREG_SCB1_INTR_M_MASK
UART_SCB__INTR_M_MASKED EQU CYREG_SCB1_INTR_M_MASKED
UART_SCB__INTR_M_SET EQU CYREG_SCB1_INTR_M_SET
UART_SCB__INTR_RX EQU CYREG_SCB1_INTR_RX
UART_SCB__INTR_RX_MASK EQU CYREG_SCB1_INTR_RX_MASK
UART_SCB__INTR_RX_MASKED EQU CYREG_SCB1_INTR_RX_MASKED
UART_SCB__INTR_RX_SET EQU CYREG_SCB1_INTR_RX_SET
UART_SCB__INTR_S EQU CYREG_SCB1_INTR_S
UART_SCB__INTR_S_MASK EQU CYREG_SCB1_INTR_S_MASK
UART_SCB__INTR_S_MASKED EQU CYREG_SCB1_INTR_S_MASKED
UART_SCB__INTR_S_SET EQU CYREG_SCB1_INTR_S_SET
UART_SCB__INTR_SPI_EC EQU CYREG_SCB1_INTR_SPI_EC
UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB1_INTR_SPI_EC_MASK
UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB1_INTR_SPI_EC_MASKED
UART_SCB__INTR_TX EQU CYREG_SCB1_INTR_TX
UART_SCB__INTR_TX_MASK EQU CYREG_SCB1_INTR_TX_MASK
UART_SCB__INTR_TX_MASKED EQU CYREG_SCB1_INTR_TX_MASKED
UART_SCB__INTR_TX_SET EQU CYREG_SCB1_INTR_TX_SET
UART_SCB__RX_CTRL EQU CYREG_SCB1_RX_CTRL
UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB1_RX_FIFO_CTRL
UART_SCB__RX_FIFO_RD EQU CYREG_SCB1_RX_FIFO_RD
UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB1_RX_FIFO_RD_SILENT
UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB1_RX_FIFO_STATUS
UART_SCB__RX_MATCH EQU CYREG_SCB1_RX_MATCH
UART_SCB__SPI_CTRL EQU CYREG_SCB1_SPI_CTRL
UART_SCB__SPI_STATUS EQU CYREG_SCB1_SPI_STATUS
UART_SCB__SS0_POSISTION EQU 0
UART_SCB__SS1_POSISTION EQU 1
UART_SCB__SS2_POSISTION EQU 2
UART_SCB__SS3_POSISTION EQU 3
UART_SCB__STATUS EQU CYREG_SCB1_STATUS
UART_SCB__TX_CTRL EQU CYREG_SCB1_TX_CTRL
UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB1_TX_FIFO_CTRL
UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB1_TX_FIFO_STATUS
UART_SCB__TX_FIFO_WR EQU CYREG_SCB1_TX_FIFO_WR
UART_SCB__UART_CTRL EQU CYREG_SCB1_UART_CTRL
UART_SCB__UART_RX_CTRL EQU CYREG_SCB1_UART_RX_CTRL
UART_SCB__UART_RX_STATUS EQU CYREG_SCB1_UART_RX_STATUS
UART_SCB__UART_TX_CTRL EQU CYREG_SCB1_UART_TX_CTRL

/* UART_SCBCLK */
UART_SCBCLK__DIVIDER_MASK EQU 0x0000FFFF
UART_SCBCLK__ENABLE EQU CYREG_CLK_DIVIDER_A00
UART_SCBCLK__ENABLE_MASK EQU 0x80000000
UART_SCBCLK__MASK EQU 0x80000000
UART_SCBCLK__REGISTER EQU CYREG_CLK_DIVIDER_A00

/* UART_tx */
UART_tx__0__DM__MASK EQU 0x38000
UART_tx__0__DM__SHIFT EQU 15
UART_tx__0__DR EQU CYREG_PRT0_DR
UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
UART_tx__0__HSIOM_MASK EQU 0x00F00000
UART_tx__0__HSIOM_SHIFT EQU 20
UART_tx__0__INTCFG EQU CYREG_PRT0_INTCFG
UART_tx__0__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_tx__0__MASK EQU 0x20
UART_tx__0__OUT_SEL EQU CYREG_UDB_PA0_CFG10
UART_tx__0__OUT_SEL_SHIFT EQU 10
UART_tx__0__OUT_SEL_VAL EQU -1
UART_tx__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_tx__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_tx__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_tx__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_tx__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_tx__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_tx__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_tx__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_tx__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_tx__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_tx__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_tx__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_tx__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_tx__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_tx__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_tx__0__PC EQU CYREG_PRT0_PC
UART_tx__0__PC2 EQU CYREG_PRT0_PC2
UART_tx__0__PORT EQU 0
UART_tx__0__PS EQU CYREG_PRT0_PS
UART_tx__0__SHIFT EQU 5
UART_tx__DR EQU CYREG_PRT0_DR
UART_tx__INTCFG EQU CYREG_PRT0_INTCFG
UART_tx__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_tx__MASK EQU 0x20
UART_tx__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_tx__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_tx__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_tx__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_tx__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_tx__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_tx__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_tx__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_tx__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_tx__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_tx__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_tx__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_tx__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_tx__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_tx__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_tx__PC EQU CYREG_PRT0_PC
UART_tx__PC2 EQU CYREG_PRT0_PC2
UART_tx__PORT EQU 0
UART_tx__PS EQU CYREG_PRT0_PS
UART_tx__SHIFT EQU 5

/* Pin_1 */
Pin_1__0__DM__MASK EQU 0x1C0000
Pin_1__0__DM__SHIFT EQU 18
Pin_1__0__DR EQU CYREG_PRT1_DR
Pin_1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
Pin_1__0__HSIOM_MASK EQU 0x0F000000
Pin_1__0__HSIOM_SHIFT EQU 24
Pin_1__0__INTCFG EQU CYREG_PRT1_INTCFG
Pin_1__0__INTSTAT EQU CYREG_PRT1_INTSTAT
Pin_1__0__MASK EQU 0x40
Pin_1__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
Pin_1__0__OUT_SEL_SHIFT EQU 12
Pin_1__0__OUT_SEL_VAL EQU 1
Pin_1__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
Pin_1__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
Pin_1__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
Pin_1__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
Pin_1__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
Pin_1__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
Pin_1__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
Pin_1__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
Pin_1__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
Pin_1__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
Pin_1__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
Pin_1__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
Pin_1__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
Pin_1__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
Pin_1__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
Pin_1__0__PC EQU CYREG_PRT1_PC
Pin_1__0__PC2 EQU CYREG_PRT1_PC2
Pin_1__0__PORT EQU 1
Pin_1__0__PS EQU CYREG_PRT1_PS
Pin_1__0__SHIFT EQU 6
Pin_1__DR EQU CYREG_PRT1_DR
Pin_1__INTCFG EQU CYREG_PRT1_INTCFG
Pin_1__INTSTAT EQU CYREG_PRT1_INTSTAT
Pin_1__MASK EQU 0x40
Pin_1__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
Pin_1__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
Pin_1__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
Pin_1__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
Pin_1__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
Pin_1__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
Pin_1__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
Pin_1__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
Pin_1__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
Pin_1__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
Pin_1__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
Pin_1__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
Pin_1__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
Pin_1__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
Pin_1__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
Pin_1__PC EQU CYREG_PRT1_PC
Pin_1__PC2 EQU CYREG_PRT1_PC2
Pin_1__PORT EQU 1
Pin_1__PS EQU CYREG_PRT1_PS
Pin_1__SHIFT EQU 6

/* Pin_col */
Pin_col__0__DM__MASK EQU 0x7000
Pin_col__0__DM__SHIFT EQU 12
Pin_col__0__DR EQU CYREG_PRT2_DR
Pin_col__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_col__0__HSIOM_MASK EQU 0x000F0000
Pin_col__0__HSIOM_SHIFT EQU 16
Pin_col__0__INTCFG EQU CYREG_PRT2_INTCFG
Pin_col__0__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_col__0__MASK EQU 0x10
Pin_col__0__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_col__0__OUT_SEL_SHIFT EQU 8
Pin_col__0__OUT_SEL_VAL EQU 1
Pin_col__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_col__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_col__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_col__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_col__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_col__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_col__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_col__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_col__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_col__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_col__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_col__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_col__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_col__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_col__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_col__0__PC EQU CYREG_PRT2_PC
Pin_col__0__PC2 EQU CYREG_PRT2_PC2
Pin_col__0__PORT EQU 2
Pin_col__0__PS EQU CYREG_PRT2_PS
Pin_col__0__SHIFT EQU 4
Pin_col__1__DM__MASK EQU 0x38000
Pin_col__1__DM__SHIFT EQU 15
Pin_col__1__DR EQU CYREG_PRT2_DR
Pin_col__1__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_col__1__HSIOM_MASK EQU 0x00F00000
Pin_col__1__HSIOM_SHIFT EQU 20
Pin_col__1__INTCFG EQU CYREG_PRT2_INTCFG
Pin_col__1__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_col__1__MASK EQU 0x20
Pin_col__1__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_col__1__OUT_SEL_SHIFT EQU 10
Pin_col__1__OUT_SEL_VAL EQU 3
Pin_col__1__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_col__1__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_col__1__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_col__1__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_col__1__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_col__1__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_col__1__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_col__1__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_col__1__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_col__1__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_col__1__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_col__1__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_col__1__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_col__1__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_col__1__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_col__1__PC EQU CYREG_PRT2_PC
Pin_col__1__PC2 EQU CYREG_PRT2_PC2
Pin_col__1__PORT EQU 2
Pin_col__1__PS EQU CYREG_PRT2_PS
Pin_col__1__SHIFT EQU 5
Pin_col__2__DM__MASK EQU 0x1C0000
Pin_col__2__DM__SHIFT EQU 18
Pin_col__2__DR EQU CYREG_PRT2_DR
Pin_col__2__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_col__2__HSIOM_MASK EQU 0x0F000000
Pin_col__2__HSIOM_SHIFT EQU 24
Pin_col__2__INTCFG EQU CYREG_PRT2_INTCFG
Pin_col__2__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_col__2__MASK EQU 0x40
Pin_col__2__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_col__2__OUT_SEL_SHIFT EQU 12
Pin_col__2__OUT_SEL_VAL EQU 2
Pin_col__2__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_col__2__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_col__2__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_col__2__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_col__2__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_col__2__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_col__2__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_col__2__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_col__2__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_col__2__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_col__2__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_col__2__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_col__2__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_col__2__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_col__2__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_col__2__PC EQU CYREG_PRT2_PC
Pin_col__2__PC2 EQU CYREG_PRT2_PC2
Pin_col__2__PORT EQU 2
Pin_col__2__PS EQU CYREG_PRT2_PS
Pin_col__2__SHIFT EQU 6
Pin_col__3__DM__MASK EQU 0xE00000
Pin_col__3__DM__SHIFT EQU 21
Pin_col__3__DR EQU CYREG_PRT2_DR
Pin_col__3__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_col__3__HSIOM_MASK EQU 0xF0000000
Pin_col__3__HSIOM_SHIFT EQU 28
Pin_col__3__INTCFG EQU CYREG_PRT2_INTCFG
Pin_col__3__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_col__3__MASK EQU 0x80
Pin_col__3__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_col__3__OUT_SEL_SHIFT EQU 14
Pin_col__3__OUT_SEL_VAL EQU 0
Pin_col__3__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_col__3__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_col__3__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_col__3__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_col__3__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_col__3__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_col__3__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_col__3__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_col__3__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_col__3__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_col__3__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_col__3__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_col__3__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_col__3__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_col__3__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_col__3__PC EQU CYREG_PRT2_PC
Pin_col__3__PC2 EQU CYREG_PRT2_PC2
Pin_col__3__PORT EQU 2
Pin_col__3__PS EQU CYREG_PRT2_PS
Pin_col__3__SHIFT EQU 7
Pin_col__DR EQU CYREG_PRT2_DR
Pin_col__INTCFG EQU CYREG_PRT2_INTCFG
Pin_col__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_col__MASK EQU 0xF0
Pin_col__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_col__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_col__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_col__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_col__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_col__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_col__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_col__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_col__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_col__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_col__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_col__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_col__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_col__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_col__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_col__PC EQU CYREG_PRT2_PC
Pin_col__PC2 EQU CYREG_PRT2_PC2
Pin_col__PORT EQU 2
Pin_col__PS EQU CYREG_PRT2_PS
Pin_col__SHIFT EQU 4

/* Pin_row */
Pin_row__0__DM__MASK EQU 0x07
Pin_row__0__DM__SHIFT EQU 0
Pin_row__0__DR EQU CYREG_PRT2_DR
Pin_row__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_row__0__HSIOM_MASK EQU 0x0000000F
Pin_row__0__HSIOM_SHIFT EQU 0
Pin_row__0__INTCFG EQU CYREG_PRT2_INTCFG
Pin_row__0__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_row__0__MASK EQU 0x01
Pin_row__0__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_row__0__OUT_SEL_SHIFT EQU 0
Pin_row__0__OUT_SEL_VAL EQU 1
Pin_row__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_row__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_row__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_row__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_row__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_row__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_row__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_row__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_row__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_row__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_row__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_row__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_row__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_row__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_row__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_row__0__PC EQU CYREG_PRT2_PC
Pin_row__0__PC2 EQU CYREG_PRT2_PC2
Pin_row__0__PORT EQU 2
Pin_row__0__PS EQU CYREG_PRT2_PS
Pin_row__0__SHIFT EQU 0
Pin_row__1__DM__MASK EQU 0x38
Pin_row__1__DM__SHIFT EQU 3
Pin_row__1__DR EQU CYREG_PRT2_DR
Pin_row__1__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_row__1__HSIOM_MASK EQU 0x000000F0
Pin_row__1__HSIOM_SHIFT EQU 4
Pin_row__1__INTCFG EQU CYREG_PRT2_INTCFG
Pin_row__1__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_row__1__MASK EQU 0x02
Pin_row__1__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_row__1__OUT_SEL_SHIFT EQU 2
Pin_row__1__OUT_SEL_VAL EQU 0
Pin_row__1__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_row__1__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_row__1__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_row__1__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_row__1__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_row__1__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_row__1__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_row__1__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_row__1__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_row__1__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_row__1__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_row__1__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_row__1__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_row__1__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_row__1__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_row__1__PC EQU CYREG_PRT2_PC
Pin_row__1__PC2 EQU CYREG_PRT2_PC2
Pin_row__1__PORT EQU 2
Pin_row__1__PS EQU CYREG_PRT2_PS
Pin_row__1__SHIFT EQU 1
Pin_row__2__DM__MASK EQU 0x1C0
Pin_row__2__DM__SHIFT EQU 6
Pin_row__2__DR EQU CYREG_PRT2_DR
Pin_row__2__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_row__2__HSIOM_MASK EQU 0x00000F00
Pin_row__2__HSIOM_SHIFT EQU 8
Pin_row__2__INTCFG EQU CYREG_PRT2_INTCFG
Pin_row__2__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_row__2__MASK EQU 0x04
Pin_row__2__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_row__2__OUT_SEL_SHIFT EQU 4
Pin_row__2__OUT_SEL_VAL EQU 2
Pin_row__2__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_row__2__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_row__2__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_row__2__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_row__2__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_row__2__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_row__2__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_row__2__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_row__2__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_row__2__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_row__2__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_row__2__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_row__2__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_row__2__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_row__2__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_row__2__PC EQU CYREG_PRT2_PC
Pin_row__2__PC2 EQU CYREG_PRT2_PC2
Pin_row__2__PORT EQU 2
Pin_row__2__PS EQU CYREG_PRT2_PS
Pin_row__2__SHIFT EQU 2
Pin_row__3__DM__MASK EQU 0xE00
Pin_row__3__DM__SHIFT EQU 9
Pin_row__3__DR EQU CYREG_PRT2_DR
Pin_row__3__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_row__3__HSIOM_MASK EQU 0x0000F000
Pin_row__3__HSIOM_SHIFT EQU 12
Pin_row__3__INTCFG EQU CYREG_PRT2_INTCFG
Pin_row__3__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_row__3__MASK EQU 0x08
Pin_row__3__OUT_SEL EQU CYREG_UDB_PA2_CFG10
Pin_row__3__OUT_SEL_SHIFT EQU 6
Pin_row__3__OUT_SEL_VAL EQU 3
Pin_row__3__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_row__3__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_row__3__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_row__3__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_row__3__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_row__3__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_row__3__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_row__3__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_row__3__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_row__3__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_row__3__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_row__3__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_row__3__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_row__3__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_row__3__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_row__3__PC EQU CYREG_PRT2_PC
Pin_row__3__PC2 EQU CYREG_PRT2_PC2
Pin_row__3__PORT EQU 2
Pin_row__3__PS EQU CYREG_PRT2_PS
Pin_row__3__SHIFT EQU 3
Pin_row__DR EQU CYREG_PRT2_DR
Pin_row__INTCFG EQU CYREG_PRT2_INTCFG
Pin_row__INTSTAT EQU CYREG_PRT2_INTSTAT
Pin_row__MASK EQU 0x0F
Pin_row__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_row__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_row__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_row__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_row__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_row__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_row__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_row__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_row__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_row__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_row__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_row__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_row__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_row__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_row__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_row__PC EQU CYREG_PRT2_PC
Pin_row__PC2 EQU CYREG_PRT2_PC2
Pin_row__PORT EQU 2
Pin_row__PS EQU CYREG_PRT2_PS
Pin_row__SHIFT EQU 0

/* col_reg */
col_reg_Sync_ctrl_reg__0__MASK EQU 0x01
col_reg_Sync_ctrl_reg__0__POS EQU 0
col_reg_Sync_ctrl_reg__1__MASK EQU 0x02
col_reg_Sync_ctrl_reg__1__POS EQU 1
col_reg_Sync_ctrl_reg__2__MASK EQU 0x04
col_reg_Sync_ctrl_reg__2__POS EQU 2
col_reg_Sync_ctrl_reg__3__MASK EQU 0x08
col_reg_Sync_ctrl_reg__3__POS EQU 3
col_reg_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL_03
col_reg_Sync_ctrl_reg__CONTROL_REG EQU CYREG_UDB_W8_CTL_03
col_reg_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_UDB_CAT16_CTL_ST_03
col_reg_Sync_ctrl_reg__COUNT_REG EQU CYREG_UDB_W8_CTL_03
col_reg_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_UDB_CAT16_CTL_ST_03
col_reg_Sync_ctrl_reg__MASK EQU 0x0F
col_reg_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK_03
col_reg_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK_03
col_reg_Sync_ctrl_reg__PERIOD_REG EQU CYREG_UDB_W8_MSK_03

/* isr_key */
isr_key__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
isr_key__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
isr_key__INTC_MASK EQU 0x01
isr_key__INTC_NUMBER EQU 0
isr_key__INTC_PRIOR_MASK EQU 0xC0
isr_key__INTC_PRIOR_NUM EQU 3
isr_key__INTC_PRIOR_REG EQU CYREG_CM0_IPR0
isr_key__INTC_SET_EN_REG EQU CYREG_CM0_ISER
isr_key__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* row_reg */
row_reg_Sync_ctrl_reg__0__MASK EQU 0x01
row_reg_Sync_ctrl_reg__0__POS EQU 0
row_reg_Sync_ctrl_reg__1__MASK EQU 0x02
row_reg_Sync_ctrl_reg__1__POS EQU 1
row_reg_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_UDB_W16_ACTL_02
row_reg_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_UDB_W16_CTL_02
row_reg_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_UDB_W16_CTL_02
row_reg_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_UDB_W16_CTL_02
row_reg_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_UDB_W16_CTL_02
row_reg_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_UDB_W16_MSK_02
row_reg_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_UDB_W16_MSK_02
row_reg_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_UDB_W16_MSK_02
row_reg_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_UDB_W16_MSK_02
row_reg_Sync_ctrl_reg__2__MASK EQU 0x04
row_reg_Sync_ctrl_reg__2__POS EQU 2
row_reg_Sync_ctrl_reg__3__MASK EQU 0x08
row_reg_Sync_ctrl_reg__3__POS EQU 3
row_reg_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL_02
row_reg_Sync_ctrl_reg__CONTROL_REG EQU CYREG_UDB_W8_CTL_02
row_reg_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_UDB_CAT16_CTL_ST_02
row_reg_Sync_ctrl_reg__COUNT_REG EQU CYREG_UDB_W8_CTL_02
row_reg_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_UDB_CAT16_CTL_ST_02
row_reg_Sync_ctrl_reg__MASK EQU 0x0F
row_reg_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK_02
row_reg_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK_02
row_reg_Sync_ctrl_reg__PERIOD_REG EQU CYREG_UDB_W8_MSK_02

/* isr_uart */
isr_uart__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
isr_uart__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
isr_uart__INTC_MASK EQU 0x800
isr_uart__INTC_NUMBER EQU 11
isr_uart__INTC_PRIOR_MASK EQU 0xC0000000
isr_uart__INTC_PRIOR_NUM EQU 3
isr_uart__INTC_PRIOR_REG EQU CYREG_CM0_IPR2
isr_uart__INTC_SET_EN_REG EQU CYREG_CM0_ISER
isr_uart__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* GlitchFilter_1 */
GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_A0_REG EQU CYREG_UDB_W16_A0_02
GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_A1_REG EQU CYREG_UDB_W16_A1_02
GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_D0_REG EQU CYREG_UDB_W16_D0_02
GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_D1_REG EQU CYREG_UDB_W16_D1_02
GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_UDB_W16_ACTL_02
GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_F0_REG EQU CYREG_UDB_W16_F0_02
GlitchFilter_1_genblk2_Counter0_DP_u0__16BIT_F1_REG EQU CYREG_UDB_W16_F1_02
GlitchFilter_1_genblk2_Counter0_DP_u0__A0_A1_REG EQU CYREG_UDB_CAT16_A_02
GlitchFilter_1_genblk2_Counter0_DP_u0__A0_REG EQU CYREG_UDB_W8_A0_02
GlitchFilter_1_genblk2_Counter0_DP_u0__A1_REG EQU CYREG_UDB_W8_A1_02
GlitchFilter_1_genblk2_Counter0_DP_u0__D0_D1_REG EQU CYREG_UDB_CAT16_D_02
GlitchFilter_1_genblk2_Counter0_DP_u0__D0_REG EQU CYREG_UDB_W8_D0_02
GlitchFilter_1_genblk2_Counter0_DP_u0__D1_REG EQU CYREG_UDB_W8_D1_02
GlitchFilter_1_genblk2_Counter0_DP_u0__DP_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL_02
GlitchFilter_1_genblk2_Counter0_DP_u0__F0_F1_REG EQU CYREG_UDB_CAT16_F_02
GlitchFilter_1_genblk2_Counter0_DP_u0__F0_REG EQU CYREG_UDB_W8_F0_02
GlitchFilter_1_genblk2_Counter0_DP_u0__F1_REG EQU CYREG_UDB_W8_F1_02
GlitchFilter_1_genblk2_Counter0_DP_u0__MSK_DP_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK_02
GlitchFilter_1_genblk2_Counter0_DP_u0__PER_DP_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK_02

/* Miscellaneous */
CYDEV_BCLK__HFCLK__HZ EQU 24000000
CYDEV_BCLK__HFCLK__KHZ EQU 24000
CYDEV_BCLK__HFCLK__MHZ EQU 24
CYDEV_BCLK__SYSCLK__HZ EQU 24000000
CYDEV_BCLK__SYSCLK__KHZ EQU 24000
CYDEV_BCLK__SYSCLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 6
CYDEV_CHIP_DIE_PSOC4A EQU 3
CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x04C81193
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 3
CYDEV_CHIP_MEMBER_4D EQU 2
CYDEV_CHIP_MEMBER_4F EQU 4
CYDEV_CHIP_MEMBER_5A EQU 6
CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4A
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4A_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0400
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD_MV EQU 3300
CYIPBLOCK_M0S8_CTBM_VERSION EQU 0
CYIPBLOCK_m0s8cpuss_VERSION EQU 0
CYIPBLOCK_m0s8csd_VERSION EQU 0
CYIPBLOCK_m0s8gpio2_VERSION EQU 0
CYIPBLOCK_m0s8hsiom4a_VERSION EQU 0
CYIPBLOCK_m0s8lcd_VERSION EQU 0
CYIPBLOCK_m0s8lpcomp_VERSION EQU 0
CYIPBLOCK_m0s8pclk_VERSION EQU 0
CYIPBLOCK_m0s8sar_VERSION EQU 0
CYIPBLOCK_m0s8scb_VERSION EQU 0
CYIPBLOCK_m0s8srssv2_VERSION EQU 1
CYIPBLOCK_m0s8tcpwm_VERSION EQU 0
CYIPBLOCK_m0s8udbif_VERSION EQU 0
CYIPBLOCK_S8_GPIO_VERSION EQU 2
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
